Metastability
Metastability refers to signals that do not assume stable 0 or 1 states for some duration of time at some point during normal operation of a design. In a multi-clock design, metastability cannot be avoided but the detrimental effects of metastability can be neutralized.
Figure - Asynchronous clocks and synchronization failure
The above figure shows a synchronization failure that occurs when a signal generated in one clock
domain is sampled too close to the rising edge of a clock signal from a second clock domain.
Synchronization failure is caused by an output going metastable and not converging to a legal
stable state by the time the output must be sampled again.
Why is metastability a problem?
The below figure shows that a metastable output that traverses
additional logic in the receiving clock domain can cause illegal signal values to be propagated
throughout the rest of the design. Since the CDC signal can fluctuate for some period of time, the
input logic in the receiving clock domain might recognize the logic level of the fluctuating signal
to be different values and hence propagate erroneous signals into the receiving clock domain.
Figure - Metastable bdat1 output propagating invalid data throughout the design
Every flip-flop that is used in any design has a specified setup and hold time, or the time in which
the data input is not legally permitted to change before and after a rising clock edge. This time window is specified as a design parameter precisely to keep a data signal from changing too close
to another synchronizing signal that could cause the output to go metastable.
Tags:
CDC
