3.0 Synchronizer
When passing signals between clock domains, an important question to ask is, do I need to sample every value of a signal that is passed from one clock domain to another?
3.1 Two synchronization scenarios
There are two scenarios that are possible when passing signals across CDC boundaries, and it is important to determine which scenario applies to your design:
(1) It is permitted to miss samples that are passed between clock domains.
(2) Every signal passed between clock domains must be sampled.
First scenario: sometimes it is not necessary to sample every value, but it is important that the sampled values are accurate. One example is the set of gray code counters used in a standard asynchronous FIFO design. In a properly designed asynchronous FIFO model, synchronized gray code counters do not need to capture every legal value from the opposite clock domain, but it is critical that sampled values be accurate to recognize when full and empty conditions have occurred.
Second scenario: a CDC signal must be properly recognized or recognized and acknowledged before a change is permitted on the CDC signal
In both of these scenarios, the CDC signals will require some form of synchronization into the receiving clock domain.
3.2 Two flip-flop synchronizer
"A synchronizer is a device that samples an asynchronous signal and outputs a version of the signal that has transitions synchronized to a local or sample clock."
Figure - Two flip-flop synchronizer
The simplest and most common synchronizer used by digital designers is a two-flip-flop synchronizer as shown in Figure
The first flip-flop samples the asynchronous input signal into the new clock domain and waits for a full clock cycle to permit any metastability on the stage-1 output signal to decay, then the stage-1 signal is sampled by the same clock into a second stage flip-flop, with the intended goal that the stage-2 signal is now a stable and valid signal synchronized and ready for distribution within the new clock domain.
It is theoretically possible for the stage-1 signal to still be sufficiently metastable by the time the signal is clocked into the second stage to cause the stage-2 output signal to also go metastable. The calculation of the probability of the time between synchronization failures (MTBF) is a function of multiple variables including the clock frequencies used to generate the input signal and to clock the synchronizing flip-flops.
For most synchronization applications, the two flip-flop synchronizer is sufficient to remove all likely metastability.
3.3 MTBF - mean time before failure
For most applications, it is important to run a calculation of the Mean Time Before Failure (MTBF) for any signal crossing a CDC boundary. Failure in this sense means a signal that is passed to a synchronizing flip-flop, goes metastable on the first stage synchronizer flip-flop, and continues to be metastable one cycle later when it is sampled into the second stage synchronizer flip-flop. Since the signal did not settle to a known value after one clock cycle, the signal could still be metastable when sampled and passed to the receiving clock domain, causing potential failures to the corresponding logic.
When calculating MTBF numbers, larger numbers are preferred over smaller numbers. Larger MTBF numbers indicate longer periods of time between potential failures, while smaller MTBF numbers indicate that metastability could happen frequently, similarly causing failures within the design.
Dally and Poulton given a good equation with very thorough analysis of the calculation that can be performed to calculate the MTBF of a synchronizer circuit. Without repeating the equation and analysis, it should be pointed out that two of the most important factors that directly impact the MTBF of a synchronizer circuit are, the sample clock frequency (how fast are signals being sampled into the receiving clock domain) and the data change frequency (how fast is the data changing that crosses the CDC boundary).
From the above partial equation, it can be seen that failures occur more frequently (shorter MTBF) in higher speed designs, or when the sampled data changes more frequently.
